Phase-locked loops are widely employed in radio, telecommunications, smartphones, computers, and other electronic applications. They can be used in circuits which function to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, or distribute precisely timed clock pulses in digital logic circuits such as microprocessors.
Such phase-locked loops typically employ asynchronous counters and dividers to divide a clock signal down to another frequency. However, asynchronous counters have a maximum operation frequency that decreases as the number of bits of the divisor used increases due to the delay in each of its stages due to ripple. In addition, power consumption increases as the number of bits of the divisor increases.
Therefore, new designs for asynchronous counters that can work at higher frequencies and consume less power are desirable.